EDD5116AGTA-4 Datasheet | Elpida Memory

Features - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture - Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver - Data inputs, outputs, and DM are synchronized with DQS - DQS is edge-aligned with data for READs; centeraligned with data for WRITEs - Differential clock inputs (CK and /CK) - DLL aligns DQ and DQS transitions with CK transitions - mands entered on each positive CK edge; data and data mask referenced to both edges of DQS - Data mask (DM) for write data Document No. E1195E20 (Ver. 2.0) Date Published February 2008 (K) Japan Printed in Japan URL: http://.elpida. ©Elpida Memory, Inc. 2007-2008 EDD5108AGTA-4, EDD5116AGTA-4 Ordering Information Part number EDD5108AGTA-4B-E EDD5108AGTA-4C-E EDD5116AGTA-4B-E EDD5116AGTA-4C-E Mask version G Organization (words × bits) 64M × 8 32M × 16 Internal banks 4 Data rate Mbps (max.) 500 500 Speed bin (CL-t RCD-t RP) DDR500B (3-3-3) DDR500C (3-4-4) DDR500B (3-3-3) DDR500C (3-4-4) Package 66-pin Plastic TSOP (II) Part Number E D D 51 08 A G TA - 4B - E Elpida Memory Environment Code E: Lead Free (Ro HS pliant) Type D: Monolithic Device Product Family D: DDR SDRAM Density / Bank 51: 512M / 4-bank Organization 08: x8 16: x16 Power Supply, Interface A: 2.5V, SSTL_2 Speed 4B: DDR500B (3-3-3) 4C: DDR500C (3-4-4) Package TA: TSOP (II) Die Rev. Speed Grade patibility Operating Frequencies Speed bin DDR500B DDR500C CL2 133MHz 133MHz CL2.5 166MHz 166MHz CL3 250MHz 250MHz .. Data Sheet E1195E20 (Ver. 2.0) EDD5108AGTA-4, EDD5116AGTA-4 Pin Configurations /xxx indicates active low signal. 66-pin Plastic TSOP(II) VDD VDD DQ0 DQ0 VDDQ VDDQ NC DQ1 DQ1 DQ2 VSSQ VSSQ NC DQ3 DQ2 DQ4 VDDQ VDDQ NC DQ5 DQ3 DQ6 VSSQ VSSQ NC DQ7 NC NC VDDQ VDDQ NC LDQS NC NC VDD VDD NC NC NC LDM /WE /WE /CAS /CAS /RAS /RAS /CS /CS NC NC BA0 BA0 BA1 BA1 A10(AP) A10(AP) A0 A0 A1 A1 A2 A2 A3 A3 VDD...