EDS5108ABTA Overview
The EDS5104AB is a 512M bits SDRAM organized as 33,554,432 words × 4 bits × 4 banks. The EDS5108AB is a 512M bits SDRAM organized as 16,777,216 words × 8 bits × 4 banks. The EDS5116AB is a 512M bits SDRAM organized as 8,388,608 words × 16 bits × 4 banks.
EDS5108ABTA Key Features
- 3.3V power supply Clock frequency: 166MHz/133MHz (max.) LVTTL interface Single pulsed /RAS 4 banks can operate simultane
- Burst read/write operation and burst read/single write operation capability
- Programmable burst length (BL): 1, 2, 4, 8, full page
- Programmable /CAS latency (CL): 2, 3
- Byte control by DQM : DQM (EDS5104AB, EDS5108AB) : UDQM, LDQM (EDS5116AB)
- Refresh cycles: 8192 refresh cycles/64ms
- 2 variations of refresh Auto refresh Self refresh