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Preliminary
EM488M3244LBB
256Mb (2M×4Bank×32) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge • Single 1.8V ±0.1V Power Supply • LVCMOS Compatible with Multiplexed Address • Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page • Programmable CAS Latency (C/L) - 2 or 3 • Data Mask (DQM) for Read / Write Masking • Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 1/2/4/8) • Burst Read with Single-bit Write Operation • Deep Power Down Mode. • Auto Refresh and Self Refresh • Special Function Support. – PASR (Partial Array Self Refresh) – Auto TCSR (Temperature Compensated Self
Refresh) • Programmable Driver Strength Control
– Full Strength or 1/2, 1/4 of Full Strength • 4,096 Refresh Cycles / 64ms (15.