Datasheet Summary
eorex
Revision History
Revision 0.1 (Dec. 2013)
- First release
Dec. 2013
.eorex. 1/18 eorex
256Mb (2M4Bank32) Synchronous DRAM
Features
- Fully Synchronous to Positive Clock Edge
- Single 3.3V 0.3V Power Supply
- LVTTL patible with Multiplexed Address
- Programmable Burst Length (B/L)
- 1, 2, 4, 8 or Full Page
- Programmable CAS Latency (C/L)
- 2 or 3
- Data Mask (DQM) for Read / Write Masking
- Programmable Wrap Sequence
- Sequential (B/L = 1/2/4/8/full Page)
- Interleave (B/L = 1/2/4/8)
- Burst Read with Single-bit Write Operation
- All Inputs are Sampled at the Rising Edge of the System Clock
- Auto Refresh and Self Refresh
- 4,096 Refresh...