XRK32510 - 3.3V PHASE-LOCK LOOP CLOCK DRIVER

Description

The XRK32510 is a high performance, low jitter, low skew clock driver.

The XRK32510 uses phase-lock loop (PLL) tecnology to synthesize the CLK_IN signal into 10 output signals (QA), synchronized in both phase and frequency.

Features

low skew, low jitter and 50% duty cycle making it a perfect fit in dual in line memory module (DIMM) board clocking, PC133 SDRAM designs and other server.

Exar Corporation

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Datasheet Details

Part number	XRK32510
Manufacturer	Exar Corporation
File Size	116.90 KB
Description	3.3V PHASE-LOCK LOOP CLOCK DRIVER
Datasheet	XRK32510 Datasheet
Additional preview pages of the XRK32510 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com xr OCTOBER 2005 XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS REV. 1.0.1 GENERAL DESCRIPTION The XRK32510 is a high performance, low jitter, low skew clock driver. The XRK32510 uses phase-lock loop (PLL) tecnology to synthesize the CLK_IN signal into 10 output signals (QA), synchronized in both phase and frequency. XRK32510 features low skew, low jitter and 50% duty cycle making it a perfect fit in dual in line memory module (DIMM) board clocking, PC133 SDRAM designs and other server applications. The 10 outputs can be disabled using the Output Enable (OE) pin. By connecting the Feedback Output (FB_OUT) signal to the Feedback Input (FB_IN) signal, the propagation delay from CLK_IN to the 10 buffered Outputs is nearly zero. FIGURE 1.

Published: Aug 22, 2007 |