XRK39910 Datasheet | Exar

DESCRIPTION The XRK39910 is a high fanout phase locked-loop clock driver intended for high performance puting and data-munications applications. It has eight zero delay LVTTL outputs. When the OE pin is held low, all the outputs are synchronously enabled. However, if OE is held high, all the outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the PE is held high, all the outputs are synchronized with the positive edge of the CLKIN. When PE is held low, all the outputs are synchronized with the negative edge of CLKIN. The FB_IN signal is pared with the input CLKIN signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. FEATURES - - - - - - - - - - - - Eight zero delay outputs 12m A balanced drive outputs Output frequency: 15MHz to 85MHz <250ps of output to output skew Low Jitter: <200ps peak-to-peak 3 skew grades External feedback, internal loop filter Selectable positive synchronization or negative edge Synchronous output enable 3-level inputs for PLL range control PLL bypass for DC testing Available in SOIC package FIGURE 2. PIN C ONFIGURATION CLKIN VDDPLL FSEL nc PE 1 2 3 4 5 6 24 23 22 21 20 19 GND Bypass nc OE VDD Q7 Q6 GND Q5 Q4 VDD FB_IN FIGURE 1. FUNCTIONAL BLOCK DIAGRAM Q0 VDD Q0 Q1 7 8 9 10 11 12 18 17 16 15 14 13 Q1 CLKIN M Ref VCO L Q2 Q3 FB_IN Feedback GND Q2 Q3 VDD Q4 FSEL- PE Bypass- Q5 Q6 Q7 OE - Tri-Level inputs Exar Corporation 48720 Kato Road, Fremont CA, 94538 - (510) 668-7000 - FAX (510) 668-7017 - .exar. 3.3V LOW SKEW PLL CLOCK DRIVER TABLE 1: ORDERING...