74LS194
Description
This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register; they feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely: Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing) Synchronous parallel loading is acplished by applying the four bits of data and taking both mode control inputs, S0 and S1, HIGH.
Key Features
- Specify by appending the suffix letter “X” to the ordering code
- Connection Diagram © 2000 Fairchild Semiconductor Corporation DS006407 .fairchildsemi
- QA0, QB0, QC0, Q D0 = The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established
- QAn, QBn, QCn, Q Dn = The level of QA, QB, QC, respectively, before the most-recent ↑ transition of the clock
- Logic Diagram .fairchildsemi
