FDMS8662 Datasheet | Fairchild Semiconductor

Features General Description - Max r DS(on) = 2.0m: at VGS = 10V, ID = 28A - Max r DS(on) = 3.0m: at VGS = 4.5V, ID = 24A - Advanced Package and Silicon bination for low r DS(on) and high efficiency - MSL1 robust package design - Ro HS pliant The FDMS8662 has been designed to minimize losses in power conversion application. Advancements in both silicon and package technologies have been bined to offer the lowest r DS(on) while maintaining excellent switching performance. Applications - Low Side for Synchronous Buck to Power Core Processor - Secondary Side Synchronous Rectifier - Low Side Switch in POL DC/DC Converter - Oring FET/ Load Switch Top Bottom Pin 1 S D5 D6 Power 56 D7 D8 4G 3S 2S 1S MOSFET Maximum Ratings TA = 25°C unless otherwise noted Symbol VDS VGS EAS PD TJ, TSTG Parameter Drain to Source Voltage Gate to Source Voltage Drain Current -Continuous (Package limited) -Continuous (Silicon limited) -Continuous -Pulsed TC = 25°C TC = 25°C TA = 25°C Single Pulse Avalanche Energy Power Dissipation TC = 25°C Power Dissipation TA = 25°C Operating and Storage Junction Temperature Range Thermal Characteristics (Note 1a) (Note 3) (Note...