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GTLP6C816A - LVTTL-to-GTLP Clock Driver

Description

The GTLP6C816A is a clock driver that provides LVTTL to GTLP signal level translation (and vice versa).

The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTL(P) logic levels.

Features

  • s Interface between LVTTL and GTLP logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down high impedance for live insertion s 1:6 fanout clock driver for LVTTL port s 1:2 fanout clock driver for GTLP port s LVTTL compatible driver and control inputs s Flow through pinout optimizes PCB layout s Open drain on GTLP to support wired-or connection s A Port source/sink.
  • 24/+24 mA s B Port sink 50 mA s.
  • 40°C to +85°C temperature capability s Low voltage vers.

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Other Datasheets by Fairchild (onsemi)

Part Number Description
GTLP6C816 GTLP-to-TTL 1:6 Clock Driver
GTLP6C817 Low Drive GTLP-to-LVTTL 1:6 Clock Driver
GTLP10B320 10-Bit LVTTL/GTLP Transceiver
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Full PDF Text Transcription

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GTLP6C816A LVTTL-to-GTLP Clock Driver August 1998 Revised August 1999 GTLP6C816A LVTTL-to-GTLP Clock Driver General Description The GTLP6C816A is a clock driver that provides LVTTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTL(P) logic levels. High speed backplane operation is a direct result of GTL(P)’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3. Fairchild’s GTL(P) has internal edge-rate control and is process, voltage, and temperature (PVT) compensated.
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