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GTLP10B320 - 10-Bit LVTTL/GTLP Transceiver

General Description

The GTLP10B320 is a 10-bit Universal bus driver and receiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL to GTLP signal level translation.

Key Features

  • s Bidirectional interface between GTLP and LVTTL logic levels s Variable edge rate control pin to select desired edge rate on GTLP port (VERC) s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Split LVTTL inputs and outputs s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s A feedback path for control and diagnostics monitoring s TTL compatible driver and control inputs s D.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path May 2001 Revised May 2001 GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path General Description The GTLP10B320 is a 10-bit Universal bus driver and receiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL to GTLP signal level translation. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.