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GTLP16617 - 17-Bit TTL/GTLP Synchronous Bus Transceiver

Datasheet Summary

Description

The GTLP16617 is a 17-bit registered synchronous bus transceiver that provides TTL to GTLP signal level translation.

It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB.

Features

  • s Bidirectional interface between GTLP and TTL logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down/off high impedance for live insertion. s External VREF pin for receiver threshold s CMOS technology for low power dissipation s 5 V tolerant inputs and outputs on the A-Port s Bus-hold data inputs on the A-Port eliminates the need for external pull-up resistors on unused inputs. s TTL compatible driver and control inputs s Flow through pinout optimizes PCB layout s O.

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Datasheet Details

Part number GTLP16617
Manufacturer Fairchild Semiconductor
File Size 74.25 KB
Description 17-Bit TTL/GTLP Synchronous Bus Transceiver
Datasheet download datasheet GTLP16617 Datasheet
Additional preview pages of the GTLP16617 datasheet.

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Full PDF Text Transcription

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GTLP16617 17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock June 1997 Revised October 1998 GTLP16617 17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock General Description The GTLP16617 is a 17-bit registered synchronous bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time.
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