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GTLP17T616 - 17-Bit LVTTL/GTLP Bus Transceiver

General Description

The GTLP17T616 is a 17-bit registered bus transceiver that provides LVTTL to GTLP signal level translation.

It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the LVTTL CLKAB.

Key Features

  • s Bidirectional interface between GTLP and LVTTL logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down high impedance for live insertion s External VREF pin for receiver threshold adjustability s BiCMOS technology for low power dissipation s Bushold data inputs on A Port eliminates the need for external pull-up resistors for unused inputs s LVTTL compatible Driver and Control inputs s Flow-through architecture optimizes PCB layout s Open drain on GTLP to support wir.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock January 2000 Revised February 2000 GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock General Description The GTLP17T616 is a 17-bit registered bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the LVTTL CLKAB. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time.