GTLP16612 Datasheet PDF - Fairchild Semiconductor CMOS 18-Bit TTL/GTLP Universal Bus Transceiver Specs

GTLP16612 - CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

Datasheet Summary

Description

The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation.

The device is designed to provide a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels.

Features

s Bidirectional interface between GTLP and TTL logic levels s Designed with Edge Rate Control Circuit to reduce output noise s VREF pin provides external supply reference voltage for receiver threshold s Submicron Core CMOS technology for low power dissipation s Special PVT Compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s 5V tolerant inputs and outputs on A-Port s Bus-Hold data inputs on A-Port to eliminate the need for externa.

Datasheet Details

Part number	GTLP16612
Manufacturer	Fairchild Semiconductor
File Size	70.00 KB
Description	CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
Datasheet	GTLP16612 Datasheet
Additional preview pages of the GTLP16612 datasheet.

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Full PDF Text Transcription

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GTLP16612 CMOS 18-Bit TTL/GTLP Universal Bus Transceiver March 1995 Revised October 1998 GTLP16612 CMOS 18-Bit TTL/GTLP Universal Bus Transceiver General Description The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation. The device is designed to provide a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control which minimizes signal settling times. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3.

Published: Mar 23, 2005 |