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GTLP16616 - 17-Bit TTL/GTLP Bus Transceiver

General Description

The GTLP16616 is a 17-bit registered bus transceiver that provides TTL to GTLP signal level translation.

It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB.

Key Features

  • s Bidirectional interface between GTLP and TTL logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down/off high impedance for live insertion s External VREF pin for receiver threshold s CMOS technology for low power dissipation s 5 V tolerant inputs and outputs on the A-Port s Bus-hold data inputs on the A-Port eliminates the need for external pull-up resistors on unused inputs. s TTL compatible driver and control inputs s Flow through pinout optimizes PCB layout s Op.

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Other Datasheets by Fairchild (now onsemi)

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock June 1997 Revised October 1998 GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock General Description The GTLP16616 is a 17-bit registered bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time.