HM62W4100HC Datasheet | Hitachi Semiconductor

Description The HM62W4100HC is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. The HM62W4100HC is packaged in 400-mil 32-pin SOJ for high density surface mounting. Features - Single supply : 3.3 V ± 0.3 V - Access time : 10 ns (max) - pletely static memory  No clock or timing strobe required - Equal access and cycle times - Directly TTL patible  All inputs and outputs - Operating current : 115 m A (max) - TTL standby current : 40 m A (max) - CMOS standby current : 5 m A (max) : 1 m A (max) (L-version) - Data retension current : 0.6 m A (max) (L-version) - Data retension voltage: 2 V (min) (L-version) - Center VCC and VSS type pinout Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Hitachi’s Sales Dept. regarding specification. HM62W4100HC Series Ordering Information Type No. HM62W4100HCJP-10 HM62W4100HCLJP-10 Access time 10 ns 10 ns Package 400-mil 32-pin plastic SOJ (CP-32DB) HM62W4100HC Series Pin Arrangement 32-pin SOJ A0 A1 A2 A3 A4 CS I/O1 VCC VSS I/O2 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 A16 A15 OE I/O4 VSS VCC I/O3 A14 A13 A12 A11 A10 NC Pin Description Pin name A0 to A19 I/O1 to I/O4 CS OE WE VCC VSS NC Function Address input Data input/output Chip select Output enable Write enable Power supply Ground No connection HM62W4100HC Series Block Diagram (LSB) A14 A13 A12 A5 A6 A7 A11 A10 A3 A1 (MSB) I/O1 . . . I/O4 VCC Row decoder 1024-row × 64-column × 16-block × 4-bit (4,194,304 bits) VSS CS Column I/O Input data control Column decoder CS WE CS (LSB) A8 A9 A19 A17 A18 A15 A0 A2 A4 A16 (MSB) OE CS HM62W4100HC...