HN58C65 Datasheet | Hitachi Semiconductor

Description The Hitachi HN58C65 is a electrically erasable and programmable ROM organized as 8192-word × 8-bit. It realizes high speed, low power consumption, and a high level of reliability, employing advanced MNOS memory technology and CMOS process and circuitry technology. It also has a 32-byte page programming function to make its erase and write operations faster. Features - - - - - - - - - - - - Single 5 V Supply On chip latches: address, data, CE, OE, WE Automatic byte write: 10 ms max Automatic page write (32 byte): 10 ms max Fast access time: 250 ns max Low power dissipation: 20 m W/MHz typ (Active) 2.0 m W typ (Standby) Data polling and Ready/ Busy Data protection circuity on power on/power off Conforms to JEDEC byte-wide standard Reliable CMOS with MNOS cell technology 105 erase/write cycles (in page mode) 10 year data retention Ordering Information Type No. HN58C65P-25 HN58C65FP-25 Note: Access Time 250 ns 250 ns Package 600 mil 28 pin plastic DIP (DP-28) 28 pin plastic SOP- 1 (FP-28D/DA) 1. T is added to the end of the type no. for a SOP of 3.0 mm (max) thickness. HN58C65 Series Pin Arrangement HN58C65P/FP Series RDY/Busy A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (Top View) VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Pin Description Pin Name A0 - A12 I/O1 - I/O7 OE CE WE VCC VSS NC RDY/Busy Function Address input Data input/output Output enable Chip enable Write enable Power (+5 V) Ground No connection Ready/ Busy HN58C65 Series Block Diagram I/O0 VCC VSS OE CE WE Control Logic and Timing I/O7 RDY/Busy High Voltage Generator I/O Buffer and Input Latch A0 A4 Address Buffer and Latch A5 A12 Y Decoder Y Gating X Decoder Memory Array Data Latch Mode Selection Pin Mode Read Standby Write Deselect Write inhibit Data polling Note: CE VIL VIH VIL VIL X X VIL OE VIL X - 1 WE VIH X VIL VIH VIH X VIH RDY/Busy High-Z High-Z High-Z to V OL High-Z I/O Dout...