HN58S65A Datasheet | Hitachi Semiconductor

Description The Hitachi HN58S65A series is electrically erasable and programmable ROM organized as 8192-word × 8-bit. It has realized high speed, low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster. Features - Single supply: 2.2 to 3.6 V - Access time: 150 ns (max) - Power dissipation  Active: 10 m W/MHz (typ)  Standby: 36 µW (max) - On-chip latches: address, data, CE, OE, WE - Automatic byte write: 15 ms (max) - Automatic page write (64 bytes): 15 ms (max) - Ready/Busy - Data polling and Toggle bit - Data protection circuit on power on/off - Conforms to JEDEC byte-wide standard - Reliable CMOS with MNOS cell technology - 105 erase/write cycles (in page mode) - 10 years data retention - Software data protection - Industrial versions (Temperature range: - 40 to + 85˚C) are also available. Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice. HN58S65A Series Ordering Information Type No. HN58S65AT-15 Access time 150 ns Package 28-pin plastic TSOP(TFP-28DB) Pin Arrangement HN58S65AT Series A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 RDY/Busy VCC WE NC A8 A9 A11 OE (Top view) Pin Description Pin name A0 to A12 I/O0 to I/O7 OE CE WE VCC VSS RDY/Busy NC Function Address input Data input/output Output enable Chip enable Write enable Power supply Ground Ready busy No connection HN58S65A Series Block Diagram I/O0 High voltage generator to VCC VSS I/O7 RDY/Busy OE CE WE Control logic and timing I/O buffer and input latch A0 to Y decoder Y...