HN58V1001 Datasheet | Hitachi Semiconductor

Description The Hitachi HN58V1001 is a electrically erasable and programmable ROM organized as 131072-word × 8bit. It has realized high speed, low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. It also has a 128-byte page programming function to make the write operations faster. Features - Single 3 V supply: 2.7 V to 5.5 V - Access time: 250 ns (max) - Power dissipation  Active: 20 m W/MHz, (typ)  Standby: 110 µW (max) - On-chip latches: address, data, CE, OE, WE - Automatic byte write: 15 ms (max) - Automatic page write (128 bytes): 15 ms (max) - Data polling and RDY/Busy - Data protection circuit on power on/off - Conforms to JEDEC byte-wide standard - Reliable CMOS with MNOS cell technology - 104 erase/write cycles (in page mode) - 10 years data retention - Software data protection - Write protection by RES pin HN58V1001 Series Ordering Information Type No. HN58V1001P-25 HN58V1001FP-25 HN58V1001T-25 Access time 250 ns 250 ns 250 ns Package 600 mil 32-pin plastic DIP (DP-32) 525 mil 32-pin plastic SOP (FP-32D) 8 × 14 mm 32-pin plastic TSOP (TFP-32DA) Pin Arrangement HN58V1001P/FP Series RDY/Busy A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 RES WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 HN58V1001T Series A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (Top view) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A4 A5 A6 A7 A12 A14 A16 RDY/Busy VCC A15 RES WE A13 A8 A9 A11 Pin Description Pin name A0 to A16 I/O0 to I/O7 OE CE WE VCC VSS RDY/Busy RES Function Address input Data input/output Output enable Chip enable Write enable Power supply Ground Ready busy Reset HN58V1001 Series Block Diagram I/O0to High voltage generator I/O7 RDY/Busy VCC VSS RES OE CE WE RES A0 to I/O buffer and input latch...