HY57V281620FLTP Datasheet | SK Hynix

description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2 / Oct. 2007 1 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620F(L/S)TP Series DESCRIPTION The Hynix HY57V281620F(L/S)TP series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V281620F(L/S)T(P) series is organized as 4banks of 2,097,152 x 16. HY57V281620F(L/S)TP is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are patible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control mand (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate mand or can be interrupted and replaced by a new burst read or write mand on any cycle. (This pipelined design is not restricted by a '2N' rule) FEATURES - - - - Voltage: VDD, VDDQ 3.3V supply voltage All device pins are patible with LVTTL interface 54 Pin TSOPII (Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM - - - - Internal four banks operation Auto refresh and self refresh 4096 Refresh cycles / 64ms - mercial Temperature (0o C to 70o C) - Industrial Temperature (-40o C to 85o C) Operating Temperature - - - - Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency; 2, 3 Clocks Burst Read Single Write operation ORDERING INFORMATION Part No....