HY57V281620HLT - (HY57V281620HC(L/S)T) 4 Banks x 2M x 16-Bits SDRAM
SK Hynix
Download the HY57V281620HLT datasheet PDF.
This datasheet also covers the HY57V281620HCT variant, as both devices belong to the same (hy57v281620hc(l/s)t) 4 banks x 2m x 16-bits sdram family and are provided as variant models within a single manufacturer datasheet.
General Description
The Hynix HY57V281620HC(L/S)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.
Key Features
Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM or LDQM Internal four banks operation.
Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst.
Note: The manufacturer provides a single datasheet file (HY57V281620HCT_HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.
Full PDF Text Transcription for HY57V281620HLT (Reference)
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HY57V281620HLT. For precise diagrams, and layout, please refer to the original PDF.
e correction www.DataSheet4U.com www.DataSheet4U.com HY57V281620HC(L/S)T 4 Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix HY57V281620HC(L/S)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V281620HC(L/S)T is organized as 4banks of 2,097,152x16 HY57V281620HC(L/S)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and
HY57V281620HLT Datasheet
