HY57V561620 Overview
The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16. The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock.
HY57V561620 Key Features
- Single 3.3V ± 0.3V power supply All device pins are patible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II wit
- Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequential Burst
- 1, 2, 4 and 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks
