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HY57V561620 Datasheet 4banks X 4m X 16bit Synchronous Dram

Manufacturer: SK Hynix

Overview: HY57V561620(L)T 4Banks x 4M x 16Bit Synchronous DRAM.

General Description

The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

HY57V561620 is organized as 4 banks of 4,194,304x16.

The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock.

Key Features

  • Single 3.3V ± 0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM and LDQM Internal four banks operation.
  • Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequential Burst.

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