HY5DS573222FP Datasheet PDF (256M(8Mx32) GDDR SDRAM) | Download Hynix Semiconductor HY5DS573222FP

HY5DS573222FP - 256M(8Mx32) GDDR SDRAM

This page provides the datasheet information for the HY5DS573222FP, a member of the HY5DS573222F 256M(8Mx32) GDDR SDRAM family.

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

The Hynix HY5DS573222F(P) guarantee until 166MHz speed at DLL_off condition 1.8V VDD and VDDQ wide range max power supply supports All inputs and outputs are compatible with SSTL_2 interface 12mm x 12mm, 144ball FBGA with 0.8mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS0 ~ DQS3) Data outputs o.

Datasheet Details

Part number	HY5DS573222FP
Manufacturer	Hynix Semiconductor
File Size	530.01 KB
Description	256M(8Mx32) GDDR SDRAM
Datasheet	HY5DS573222FP Datasheet
Additional preview pages of the HY5DS573222FP datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com HY5DS573222F(P) 256M(8Mx32) GDDR SDRAM HY5DS573222F(P) This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Feb. 2005 1 DataSheet 4 U .com www.DataSheet4U.com 1HY5DS573222F(P) Revision History No. 0.1 0.2 0.3 0.4 0.5 1.0 Defined Target Spec. Supports Lead free parts for each speed grade CL, AC parameter, IDD5 change CL, tCK_max, tRAS, tDAL change & Comment of DLL_off condition 1) Changed IDD & VDD_max 2) Changed tRCDWR, tWR, CL, tCK_max at 350Mhz speed bin Version 1.0 Release History Draft Date Mar. 2004 Apr. 2004 Apr. 2004 Jun. 2004 Oct. 2004 Feb. 2005 Remark Rev. 1.0 / Feb. 2005 2 DataSheet 4 U .

Published: Oct 13, 2006 |