HY5DU121622B Datasheet PDF (512 Mb DDR SDRAM) | Download Hynix Semiconductor HY5DU121622B

HY5DU121622B - 512 Mb DDR SDRAM

This page provides the datasheet information for the HY5DU121622B, a member of the HY5DU121622 512 Mb DDR SDRAM family.

Description

and is subject to change without notice.

Hynix semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL ali.

Datasheet Details

Part number	HY5DU121622B
Manufacturer	Hynix Semiconductor
File Size	407.17 KB
Description	512 Mb DDR SDRAM
Datasheet	HY5DU121622B Datasheet
Additional preview pages of the HY5DU121622B datasheet.

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Full PDF Text Transcription

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HY5DU12422B(L)TP HY5DU12822B(L)TP HY5DU121622B(L)TP 512Mb DDR SDRAM HY5DU12422B(L)TP HY5DU12822B(L)TP HY5DU121622B(L)TP This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.1 / May 2004 1 HY5DU12422B(L)TP HY5DU12822B(L)TP HY5DU121622B(L)TP Revision History Revision No. 0.1 History Initial Draft Draft Date May 2004 Remark Rev. 0.

Published: Oct 1, 2005 |