HY5DU283222AF Datasheet | SK Hynix

description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.7 / Jun. 2004 1 Revision History Revision No. 0.1 0.11 0.2 0.3 Defined target spec. 500MHz speed bin added Defined IDD specification 1) Added 222MHz with CL3 and t CK_max=10ns at HY5DU283222AF-36 2) Changed VDD_min value of HY5DU283222AF-36 from 2.375V to 2.2V 3) Changed AC parameters value of HY5DU283222AF-28/33 - t RCDRD/t RP : from 6 t CK to 5 t CK - t DAL : from 9 t CK to 8 t CK - t RFC : from 19 t CK to 17 t CK 4) Changed IDD2N target specification 5) Changed t CK_max value of HY5DU283222AF-33/36 from 6ns to 10ns Changed CAS Latency of HY5DU283222AF-28 from CL5 to CL4 Changed t RAS_max Value from 120K to 100K in All Frequency Insert Overshoot/ Under Specification Insert t DSS/ t DSH parameter Added 250MHz/ 200MHz speed bin History Draft Date Nov. 2002 Dec. 2002 Feb. 2003 Mar. 2003 Remark 0.4 0.5 0.6 0.7 June 2003 Aug. 2003 Sep. 2003 Jun. 2004 Rev. 0.7 / Jun. 2004 HY5DU283222AF DESCRIPTION The Hynix HY5DU283222 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth. The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are patible with SSTL_2. FEATURES - - - - - - - - 2.5V +/- 5% VDD and VDDQ power supply supports 300 / 275 / 250 / 200 MHz 2.8V +/- 5% VDD and VDDQ power supply supports 500/450/400/350MHz All inputs and outputs are patible with SSTL_2 interface 12mm x 12mm, 144ball FBGA with...