HY5DU283222Q Datasheet | SK Hynix

description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2/Oct. 02 1 Revision History No. History 1) Changed some AC parameters a) t AC : Changed from 0.7ns to 0.9ns b) t DQSCK : Changed from 0.6ns to 0.7ns c) t RCD/t RP : Changed from 4clks to 5clks at 222MHz and from 3clks to 4clks at 200/183MHz 1) 2) 3) 4) 0.5 Removed 166MHz part from speed bin Defined IDD specification Defined AC parameters of 250MHz part Changed Pin Capacitance a) Input Clock capacitance : Changed from 2/3p F to 1.7/2.7p F (min/max) b) All other Input-only pins capacitance : Changed from 2/3p F to 1.7/2.7p F (min/max) c) Input/Output capacitance (DQ, DQS, DM) : Changed from 4/5p F to 3.7/4.7p F (min/max) 5) Changed some AC parameters a) t IS/t IH : Changed from 0.9ns to 1.0ns b) t DS/t DH : Changed from 0.45ns to 0.5ns 6) Changed VIH/VIL from Vref +/- 0.31V to Vref +/- 0.35V 1) Changed VIH/VIL from Vref +/- 0.35V to Vref +/- 0.45V 2) Change t CK_max from 5.5ns to 6ns at 250/222MHz and from 10ns to 7ns at 200/183MHz 1) Changed some AC parameters a) t QHS : Changed from 0.75ns to 0.45ns at 200/183MHz b) t DS/t DH : Changed from 0.5ns to 0.45ns 1) t RCD/t RP of 3clocks at 183/200MHz at single bank operation defined 2) t CK Max of 200/183MHz part changed from 7ns to 8ns 1) Power dissipation SPEC. changed from 1W to 2W 2) 200MHz IDD4 SPEC changed from 370m A to 300m A 3) Output Load circuit updated 1) 200/183MHz of t CK max changed from 8ns to 10ns 1) Input leakage current changed from +/-5u A to +/-2u A 1) Added 200MHz with CL3 at 250/222MHz speed bin 2) 200MHz IDD4 SPEC changed from 300m A to 370m A Date Remark Jun. 2001 Aug. 2001 Oct. 2001 0.7 0.8 0.9 1.0 1.1 1.2 Oct. 2001 Nov. 2001 Dec. 2001 May. 2002 May. 2002 Oct. 2002 Rev. 1.2/Oct. 02 HY5DU283222Q DESCRIPTION The Hynix HY5DU283222Q is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for...