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HY5DU283222BF - 128M(4Mx32) GDDR SDRAM

General Description

and is subject to change without notice.

responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • The Hynix HY5DU283222BF(P) guarantee until 200MHz speed at DLL_off condition.
  • 2.5V VDD and VDDQ wide range max power supply supports.
  • All inputs and outputs are compatible with SSTL_2 interface.
  • 12mm x 12mm, 144ball FBGA with 0.8mm pin pitch.
  • Fully differential clock inputs (CK, /CK) operation.
  • Double data rate interface.
  • Source synchronous - data transaction aligned to bidirectional data strobe (DQS0 ~ DQS3).
  • Data outputs.

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Full PDF Text Transcription for HY5DU283222BF (Reference)

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HY5DU283222BF(P) 128M(4Mx32) GDDR SDRAM HY5DU283222BF(P) This document is a general product description and is subject to change without notice. Hynix Semiconductor does ...

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ion and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Feb. 2005 1 1HY5DU283222BF(P) Revision History No. History 0.1 1) Defined Target Spec. 0.2 1) Added 200MHz speed bin 0.3 1) Changed Cas Latency to 4 clock from 5 clock at 300Mhz/275Mhz/ 250Mhz speed bin 0.4 1) Changed IDD & 500Mhz speed bin insert, 2) Changed tRCDWR, tWR at 450Mhz speed bin 1.0 1) Changed IDD Spec. 2) Changed CAS Latency to 4 clock from 5 clock at 350MHz speed bin Draft Date Jun. 2004 Jun. 2004 Sep. 2004 Remark Oct. 2004 Feb. 2005 Rev.

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