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HY5DV281622DT - 128M(8Mx16) GDDR SDRAM

General Description

and is subject to change without notice.

Hynix Electronics does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • 3.3V for VDD and 2.5V for VDDQ power supply All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O Data outputs on DQS edges when.

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www.DataSheet4U.com HY5DV281622DT 128M(8Mx16) GDDR SDRAM HY5DV281622DT This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5 / Aug. 2003 HY5DV281622DT Revision History Revision No. 0.1 0.2 0.3 0.4 0.5 History Defined Preliminary Specification Defined Target AC, DC spec. Changed tCK_max. value of HY5DV281622DT-4/5/6 from 7.5ns to 7.0ns Changed VDD/VDDQ max range of HY5DV281622DT-33/36 Changed tRAS_max Value from 120K to 100K in All Frequency Draft Date May. 2002 Nov. 2002 Feb. 2003 Aug. 2003 Aug. 2003 Remark Rev. 0.5 / Aug.