HY5DV651622 Description
The Hynix HY5DV651622 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point to point applications which require high bandwidth. HY5DV651622 is organized as 4 banks of 1,048,576x16. HY5DV651622 offers fully synchronous operations referenced to both rising and falling edges of the clock.
HY5DV651622 Key Features
- 3.3V for VDD and 2.5V for VDDQ power supply
- All inputs and outputs are patible with SSTL_2 interface
- Data strobes synchronized with output data for read and input data for write
- JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
- Delay Locked Loop(DLL) installed with DLL reset mode
- Fully differential clock operations(CLK & CLK)
- Write mask byte controls by LDM and UDM
- All addresses and control inputs except Data, Data
- Programmable CAS Latency 2 / 3 supported
- Write Operations with 1 Clock Write Latency
HY5DV651622 Applications
- 3.3V for VDD and 2.5V for VDDQ power supply
- All inputs and outputs are patible with SSTL_2 interface
- Data strobes synchronized with output data for read and input data for write
- JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
- Delay Locked Loop(DLL) installed with DLL reset mode