IS61WV6416DBLL Datasheet | ISSI

IS61WV6416DALL/DALS IS61WV6416DBLL/DBLS IS64WV6416DBLL/DBLS 64K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM MARCH 2020 Features HIGH SPEED: (IS61/64WV6416DALL/DBLL) - High-speed access time: 8, 10, 12, 20 ns - Low Active Power: 135 m W (typical) - Low Standby Power: 12 µW (typical) CMOS standby LOW POWER: (IS61/64WV6416DALS/DBLS) - High-speed access time: 25, 35 ns - Low Active Power: 55 m W (typical) - Low Standby Power: 12 µW (typical) CMOS standby - Single power supply - Vdd 1.65V to 2.2V (IS61WV6416DAxx) - Vdd 2.4V to 3.6V (IS61/64WV6416DBxx) - Fully static operation: no clock or refresh required - Three state outputs - Data control for upper and lower bytes - Industrial and Automotive temperature support - Lead-free available DESCRIPTION The ISSI IS61WV6416DAxx/DBxx and IS64WV6416DBxx are high-speed, 1,048,576-bit static RAMs organized as 65,536 words by 16 bits. It is fabricated using ISSI's high- performance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61WV6416DAxx/DBxx and IS64WV6416DBxx are packaged in the JEDEC standard 44-pin TSOP Type II, 44-pin 400-mil SOJ and 48-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A15 DECODER VDD...