ICS9112CM-18 Datasheet PDF (Zero Delay / Low Skew Buffer) | Download Integrated Circuit Systems ICS9112CM-18

ICS9112CM-18 - Zero Delay / Low Skew Buffer

Datasheet Summary

Description

The ICS9112CM-18 is a low jitter, low skew, high performance Phase Lock Loop (PLL) based zero delay buffer for high speed applications.

Based on ICS’ proprietary low jitter PLL techniques, the device provides eight low skew outputs at speeds up to 160 MHz at 3.3V.

Features

Packaged in 16 pin SOIC Zero input-output delay Four 1X outputs plus four 1/2X outputs Output to output skew is less than 250 ps Output clocks up to 160 MHz at 3.3V Ability to generate 2X the input Full CMOS outputs with 18 mA output drive capability at TTL levels at 3.3V spectrum clock generators.
Spread SmartTM technology works with spread.
Advanced, low power, sub micron CMOS process.
Operating v.

Datasheet Details

Part number	ICS9112CM-18
Manufacturer	Integrated Circuit Systems
File Size	107.03 KB
Description	Zero Delay / Low Skew Buffer
Datasheet	ICS9112CM-18 Datasheet
Additional preview pages of the ICS9112CM-18 datasheet.

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Full PDF Text Transcription

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Description w w The ICS9112CM-18 is a low jitter, low skew, high performance Phase Lock Loop (PLL) based zero delay buffer for high speed applications. Based on ICS’ proprietary low jitter PLL techniques, the device provides eight low skew outputs at speeds up to 160 MHz at 3.3V. The ICS9112-18 includes a bank of four outputs running at 1/2X. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of all eight outputs. Compared to competitive CMOS devices, the ICS9112CM-18 has the lowest jitter. a D . w ta Sh ee U 4 t .

Published: Feb 10, 2006 |