MK2049-35 Description
The MK2049-35 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-35 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other munications frequencies. This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in munications systems.
MK2049-35 Key Features
- Packaged in 20 pin SOIC
- 3.3 V ±5% operation
- Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter G
- Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz
- Locks to 8 kHz ±100 ppm (External mode)
- Buffer Mode allows jitter attenuation of 10-50 MHz input and x1/x0.5 or x1/x2 outputs
- Exact internal ratios enable zero ppm error
- Output clock rates include T1, E1, T3, E3, and OC3 submultiples
- 525 Race Street
- San Jose