IDTCSPU877A
1 to 10 differential clock distribution
Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications
Operating frequency: 125MHz to 270MHz
Very low skew: ≤40ps
Very low jitter: ≤40ps
1.8V AVDD and 1.8V VDDQ
Full PDF Text Transcription for IDTCSPU877A (Reference)
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IDTCSPU877A. For precise diagrams, and layout, please refer to the original PDF.
RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER FEATURES: DESCRIPTION: IDTCSPU877A • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 270MHz • Very low skew: ≤40ps • Very low jitter: ≤40ps • 1.8V AVDD and 1.8V VDDQ • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 52-Ball VFBGA and 40-pin MLF packages APPLICATIONS: • Meets or exceeds JEDEC standard 82.