IS62WV2568ALL Datasheet | ISSI

FEATURES - High-speed access time: 55ns, 70ns - CMOS low power operation - 36 m W (typical) operating - 9 µW (typical) CMOS standby - TTL patible interface levels - Single power supply - 1.65V--2.2V VCC (62WV2568ALL) - 2.5V--3.6V VCC (62WV2568BLL) - Fully static operation: no clock or refresh required - Three state outputs - Industrial temperature available - Lead-free available DESCRIPTION The ISSI IS62WV2568ALL / IS62WV2568BLL are highspeed, 2M bit static RAMs organized as 256K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62WV2568ALL and IS62WV2568BLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I), s TSOP (TYPE I), and 36-pin mini BGA. FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 8 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CS2 CS1 OE WE CONTROL CIRCUIT Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. - .issi. - 1-800-379-4774 Rev. B 06/20/05 IS62WV2568ALL, PIN .. DESCRIPTIONS A0-A17 CS1 CS2 OE WE I/O0-I/O7 NC Vcc GND IS62WV2568BLL ISSI ® Add...