MT48LC2M32B2 Datasheet | Micron Technology

SDR SDRAM - 512K x 32 x 4 Banks 64Mb: x32 SDRAM Features Features - PC100-pliant - Fully synchronous; all signals registered on positive edge of system clock - Internal pipelined operation; column address can be changed every clock cycle - Internal banks for hiding row access/precharge - Programmable burst lengths: 1, 2, 4, 8, or full page - Auto precharge, includes concurrent auto precharge and auto refresh modes - Self refresh mode (not available on AT devices) - Auto refresh - 64ms, 4096-cycle refresh (mercial and industrial) - 16ms, 4096-cycle refresh (automotive) - LVTTL-patible inputs and outputs - Single 3.3V ±0.3V power supply - Supports CAS latency (CL) of...