MT48LC2M8A Datasheet | Micron Technology

16 MEG: x4, x8 SDRAM SYNCHRONOUS DRAM Features - PC100-pliant; includes CONCURRENT AUTO PRECHARGE - Fully synchronous; all signals registered on positive edge of system clock - Internal pipelined operation; column address can be changed every clock cycle - Internal banks for hiding row access/precharge - Programmable burst lengths: 1, 2, 4, 8, or full page - Auto Precharge and Auto Refresh Modes - Self Refresh Mode - 64ms, 4,096-cycle refresh - LVTTL-patible inputs and outputs - Single +3.3V ±0.3V power supply - Longer lead TSOP for improved reliability (OCPL- ) - One- and two-clock WRITE recovery (tWR) versions MT48LC4M4A1/A2 S - 2 Meg x 4 x 2 banks MT48LC2M8A1/A2 S - 1 Meg x 8 x 2...