SY100S324 Datasheet | Micrel Semiconductor

Micrel, Inc. NOT REMENDED FOR NEW DESIGNS LOW POWER HEX TTL-to-ECL TRANSLATOR Features DESCRIPTION s Max. propagation delay of 1.4ns s IEE min. of - 70m A s Industry standard 100K ECL levels s Extended supply voltage option: VEE = - 4.2V to - 5.5V s Differential outputs s Voltage and temperature pensation for improved noise immunity s Internal 75kΩ input pull-down resistors s Twice as fast as Fairchild’s 324 s Function and pinout patible with Fairchild F100K s Available in 28-pin PLCC package The SY100S324 is a hex translator designed to convert TTL logic levels to 100K ECL levels. The inputs are TTL patible with differential outputs that can either be used as an inverting/non-inverting translator or as differential line drivers. A mon Enable (E), when LOW, holds all inverting outputs HIGH and holds all noninverting outputs LOW. When used in the differential mode, due to its high mon mode rejection, it overes voltage gradients between the TTL and ECL ground systems. The VEE and VTTL power may be applied in either order. BLOCK DIAGRAM E D0 D1 D2 D3 D4 D5 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 PIN NAMES Pin D0- D5 E Q0- Q5 Q0- Q5 VEES VTTL VCCA Function Data Inputs Enable Inputs Data Outputs plementary Data Outputs VEE Substrate TTL VCC Power Supply VCCO for ECL Outputs M9999-042307 hbwhelp@micrel. or (408) 955-1690 Rev.: I Amendment: /0 Issue Date: April 2007 Micrel, Inc. PACKAGE/ORDERING INFORMATION Q1 Q1 Q0 VEES Q0 D2 D1 Q2 Q2 VCC VCC VCCA VCCA...