SY100S341 Datasheet | Micrel Semiconductor

Micrel, Inc. NOT REMENDED FOR NEW DESIGNS 8-BIT SHIFT REGISTER Features DESCRIPTION s Max. shift frequency of 600MHz s Max. Clock to Q delay of 1200ps s IEE min. of - 150m A s Industry standard 100K ECL levels s Extended supply voltage option: VEE = - 4.2V to - 5.5V s Voltage and temperature pensation for improved noise immunity s Internal 75kΩ input pull-down resistors s 70% faster than Fairchild 300K at lower power s Function and pinout patible with Fairchild F100K s Available in 28-pin PLCC package The SY100S341 offer eight D-type, edge-triggered flipflops with both individual inputs for parallel operation as well as serial inputs for bidirectional shifting, and are designed for use in high-performance ECL systems. Data is clocked into the flip-flops on the rising edge of the clock. The mode of operation is selected by two Select inputs (S0, S1) which determine if the device performs a shift, hold or parallel entry function, as described in the Truth Table. The inputs on these devices have 75kΩ pull-down resistors. PIN NAMES Label CP S0 - S1 D0 - D7 P0 - P7 Q0 - Q7 VEES VCCA Function Clock Pulse Input Select Inputs Serial Inputs Parallel Inputs Data Outputs VEE Substrate VCCO for ECL Outputs M9999-042307 hbwhelp@micrel. or (408) 955-1690 Rev.: I Amendment: /0 Issue Date: April 2007 Micrel, Inc. PACKAGE/ORDERING INFORMATION P5 P6 P7 VEES D7 Q7 Q6 Ordering Information 11 10 9 8 7 6 5 Part Number Package...