SY89825U Datasheet | Micrel Semiconductor

FEATURES s LVPECL or LVDS input to 22 LVPECL outputs s 100K ECL patible outputs s LVDS input includes 100Ω termination s Guaranteed AC parameters over voltage: - > 2GHz f MAX (toggle) - < 35ps max. ch-ch skew s Low voltage operation: 2.5V, 3.3V s Temperature range: - 40°C to +85°C s Output enable pin s Available in a 64-Pin EPAD-TQFP APPLICATIONS s High-performance PCs s Workstations s Parallel processor-based systems s Other high-performance puting s munications Precision Edge® DESCRIPTION The SY89825U is a High Performance Bus Clock Driver with 22 differential LVPECL output pairs. This part is designed for use in low voltage (2.5V, 3.3V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either LVDS or LVPECL by the CLK_SEL pin. The LVDS input includes a 100Ω internal termination, thus eliminating the need for external termination. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control. The SY89825U features low pin-to-pin skew (35ps max.) - performance previously unachievable in a standard product having such a high number of outputs. The SY89825U is available in a single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew. Precision Edge is a registered trademark of Micrel, Inc. M9999-011907 hbwhelp@micrel. or (408) 955-1690 Rev.: D Amendment: /0 Issue Date: January 2007 Micrel, Inc. Precision Edge® SY89825U PACKAGE/ORDERING INFORMATION Ordering Information(1) VCCO /Q6 Q6 /Q5 Q5 /Q4 Q4 /Q3 Q3 /Q2 Q2 /Q1 Q1 /Q0 Q0 VCCO VCCO NC NC VCCI LVDS_CLK /LVDS_CLK CLK_SEL LVPECL_CLK...