SY89826L Datasheet | Micrel Semiconductor

FEATURES s High-performance, 1GHz LVDS fanout buffer/ translator s 22 differential LVDS output pairs s Guaranteed AC parameters over temperature and voltage: - > 1GHz f MAX - < 50ps within device skew - < 400ps tr / tf time s Low jitter performance - < 1ps (rms) cycle-to-cycle jitter - < 1ps (pk-pk) total jitter s 2:1 mux input accepts LVDS and LVPECL 3.3V supply voltage s LVDS input includes internal 100Ω termination s Output enable function s Available in a 64-Pin EPAD-TQFP Precision Edge® DESCRIPTION APPLICATIONS s Enterprise networking s High-end servers s munications The SY89826L is a precision fanout buffer with 22 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination. The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL pin. The OE (Output Enable) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The SY89826L features a low pin-to-pin skew of less than 50ps- performance previously unachievable in a standard product having such a high number of outputs. The SY89826L is available in a single space saving package, .. enabling a lower overall cost solution. FUNCTIONAL BLOCK DIAGRAM 100Ω internal input termination CLK_SEL LVDS_CLK 22 LVDS patible outputs TRUTH TABLE OE(1) 0 0 1 22 22 CLK_SEL 0 1 0 1 Q0 - Q21 LOW LOW LVDS_CLK LVPECL_CLK /Q0 - /Q21 HIGH HIGH /LVDS_CLK /LVPECL_CLK /LVDS_CLK Q0 - Q21 /Q0 - /Q21 LVPECL_CLK NOTE: 1. The OE (output enable) signal is synchronized with the low level of the LVDS_CLK and LVPECL_CLK signal. /LVPECL_CLK LEN Q Precision Edge is a registered trademark of Micrel, Inc....