Description
17
Precise Frequency Monitor (PFM)
18
Guard Soak Timer (GST)
31
Figure 14 "Typical Power-Up Reset and
Configuration Circuit"
32
5.1, “ZL30167 Configuration programming“
93
Register Name: phasemem_limit_ref0
130 Register Name: dpll0_df_offset
173 13.0, “Package Markings“
Change Included
Features
- Two independent clock channels.
- Two programmable digital PLLs/Numerically Controlled Oscillators (NCOs).
- Four precision synthesizers generate any clockrate from 1 Hz to 750 MHz with low jitter for 10 G PHYs.
- Programmable digital PLLs synchronize to any clock rate from 1 kHz to 750 MHz.
- Automatic hitless reference switching and digital holdover on reference fail.
- Nine input references configurable as single ended or differential and two singl.
ZL30167 Datasheet
