ZL30165 Datasheet | Microsemi

Features - Four independent clock channels - Four programmable digital PLLs/Numerically Controlled Oscillators (NCOs) - Programmable synthesizers generate any clockrate from 1 k Hz to 750 MHz - Four precision synthesizers generate clocks with low jitter of 0.63 ps RMS for 10 G PHYs - Programmable digital PLLs synchronize to any clock rate from 1 k Hz to 750 MHz - Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates - Digital PLLs filter jitter at 5.2 Hz, 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz - Automatic hitless reference switching and digital holdover on reference fail - Eight reference inputs configurable as single ended or differential Ordering Information ZL30165GDG2 144 Pin LBGA March 2015 Trays Pb Free Tin/Silver/Copper -40o C to +85o C Package Size: 13 x 13 mm - Eight LVPECL outputs and eight LVCMOS outputs - Operates from a single crystal resonator or clock oscillator - Customer defined default device configuration available via OTP (One Time Programmable) memory, including input/output frequencies - Dynamically configurable via SPI/I2C interface and volatile configuration registers Microsemi Corporation Copyright 2015, Microsemi Corporation. All Rights Reserved. Applications - OTN muxponders and transponders - 10 Gigabit line cards - Synchronous Ethernet, 10 GBASE-R and 10 GBASE-W - SONET/SDH, Fibre Channel, XAUI Data Sheet Zarlink Semiconductor Inc. Data Sheet Change History Below are the changes from the February 2014 issue to the March 2015 issue: Page 1 Item Added Features Bullet GPIO pin description Precise Frequency Monitor...