ZL30168 Description
Precise Frequency Monitor (PFM) Guard Soak Timer (GST) Figure 14 "Typical Power-Up Reset and Configuration Circuit" 5.1, “ZL30168 Configuration programming“ Register Name: phasemem_limit_ref0 127 Register Name:.
ZL30168 Key Features
- Four independent clock channels
- Programmable synthesizers generate any clockrate from 1 Hz to 750 MHz
- Four precision synthesizers generate clocks with maximum jitter below 0.63 ps RMS
- Four programmable digital PLLs/Numerically Controlled Oscillators (NCOs)/OTN clock generators based on buffer-fill level
- Programmable digital PLLs synchronize to any clock rate from 1 kHz to 750 MHz
- Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
- Digital PLLs filter jitter with bandwidths from 5 to 896 Hz
- Automatic hitless reference switching and digital holdover on reference fail
- Eight reference inputs configurable as single ended or differential
- 40oC to +85oC