ZL30163 Datasheet | Microsemi

Features - Fully pliant SEC (G.813) and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL) - Two programmable DPLLs/Numerically Controlled Oscillators (NCOs) synchronize to any clock rate from 1 Hz to 750 MHz - Four programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with maximum jitter below 0.62 ps RMS - Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates - DPLLs filter jitter from 0.1 m Hz up to 1 k Hz - Automatic hitless reference switching and digital holdover on reference fail - Nine input references configurable as single ended or differential and two single ended input references - Any input reference can be fed with sync (frame pulse) or clock May 2013 Ordering Information ZL30163GDG2 144 Pin LBGA Trays Pb Free Tin/Silver/Copper -40o C to +85o C Package Size: 13 x 13 mm - Programmable DPLLs can synchronize to sync pulse and sync pulse/clock pair - Eight LVPECL outputs and eight LVCMOS outputs - Operates from a single crystal resonator or clock oscillator - Field programmable via the SPI/I2C interface Applications - Sync E/SONET/SDH Timing Cards - Synchronous Ethernet, 10 GBASE-R and 10 GBASE-W - SONET/SDH, Fibre Channel, XAUI Osci Osco Ref0 Ref1 Ref2 Ref3 Ref4 Ref5 Ref6 Ref7 Ref8 Ref9 Ref10 Master Clock Diff / Single Ended Fr0= Br0- Kr0- Mr0/Nr0 Diff / Single Ended Fr1= Br1- Kr1- Mr1/Nr1 Diff / Single Ended Fr2= Br2- Kr2- Mr2/Nr2 Diff / Single Ended Fr3= Br3- Kr3- Mr3/Nr3 Diff / Single Ended Fr4= Br4- Kr4- Mr4/Nr4 Diff / Single Ended Fr5= Br5- Kr5- Mr5/Nr5 Diff / Single Ended Fr6= Br6- Kr6- Mr6/Nr6 Diff / Single Ended Fr7= Br7- Kr7- Mr7/Nr7 Diff / Single Ended Fr8= Br8- Kr8- Mr8/Nr8 Single Ended Fr9= Br9- Kr9- Mr9/Nr9 Single Ended Fr10= Br10- Kr10- Mr10/Nr10 JTAG Reference Monitors DPLL0/NCO0 Select Loop band., Phase slope limit DPLL1/NCO1 Select Loop band., Phase slope limit State...