Microsemi ZL30161
The positive and negative pair of these inputs accepts a differential input signal. The refx_p input terminal accepts a CMOS input reference.| Part No. | ZL30161 |
|---|---|
| Datasheet | ZL30161 Download |
| Manufacturer |  Microsemi |
| Description | Network Synchronization Clock Translator |
| Buy | Stock & Price |
FEATURES
● Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL)● Programmable DPLL/Numerically Controlled Oscillators (NCO)
● Synchronizes to any clock rate from 1 Hz to 750 MHz
● Three programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with maximum jitter below 0.62 ps rms
● Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
● Digital PLL filters jitter from 0.1 mHz up to 1 kHz
● Automatic hitless reference switching and digital holdover on reference fail
● Nine input references configurable as single ended or differential and two single ended input references May 2013 Ordering Information ZL30161GDG2 144 Pin LBGA Trays Pb Free Tin/Silver/Copper -40oC to +85oC Package Size: 13 x 13 mm
● Any input reference can be fed with sync (frame pulse) or clock
● Programmable DPLL can synchronize to sync pulse and sync/clock pair.
● Six LVPECL outputs and six LVCMOS outputs...
