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DSP56857 - 120 MIPS Hybrid Processor

Download the DSP56857 datasheet PDF. This datasheet also covers the DSP variant, as both devices belong to the same 120 mips hybrid processor family and are provided as variant models within a single manufacturer datasheet.

General Description

120 MIPS at 120MHz 40K x 16-bit Program SRAM 24K x 16-bit Data SRAM 1K x 16-bit Boot ROM Six (6) independent channels of DMA Two (2) Enhanced Synchronous Serial Interfaces (ESSI) Two (2) Serial Communication Interfaces (SCI)

Key Features

  • 1.1.1.
  • Digital Signal Processing Core Efficient 16-bit engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Four (4) 36-bit accumulators including extension bits 16-bit bidirectional shifter Parallel instruction set with uni.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DSP-56857.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
56857 Data Sheet Technical Data www.DataSheet4U.com 56800E 16-bit Digital Signal Controllers DSP56857 Rev. 6 01/2007 freescale.com www.DataSheet4U.