Description
120 MIPS at 120MHz - 40K x 16-bit Program SRAM - 24K x 16-bit Data SRAM - 1K x 16-bit Boot ROM - Six (6) independent channels of DMA - Two (2) Enhanced Synchronous Serial Interfaces (ESSI) - Two (2) Serial munication Interfaces (SCI) - Serial Port Interface (SPI) - Four (4) dedicated GPIO - 8-bit Parallel Host Interface - General Purpose 16-bit Quad Timer - JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging - puter Operating Properly (COP)/Watchdog Timer - Time-of-Day (TOD) - 100 LQFP package - Up to 47 GPIO 6 VDDIO 12 VDD 8 VSSIO 12 VSS VDDA 5 VSSA 2 JTAG/ Enhanced OnCE Program Controller and Hardware Looping Unit Address Generation Unit 16-Bit DSP56800E Core Data ALU 16 x 16 + 36 Æ 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Bit Manipulation Unit.
Key Features
- Memory Harvard architecture permits up to three (3) simultaneous accesses to program and data memory On-Chip Memory
- 40K × 16-bit Program RAM
- 24K × 16-bit Data RAM
- 1K × 16-bit Boot ROM
- Chip Select Logic used as dedicated GPIO 1.1.3
