DSP56857 - 120 MIPS Hybrid Processor

This page provides the datasheet information for the DSP56857, a member of the DSP 120 MIPS Hybrid Processor family.

Description

120 MIPS at 120MHz 40K x 16-bit Program SRAM 24K x 16-bit Data SRAM 1K x 16-bit Boot ROM Six (6) independent channels of DMA Two (2) Enhanced Synchronous Serial Interfaces (ESSI) Two (2) Serial Communication Interfaces (SCI)

Features

1.1.1.
Digital Signal Processing Core Efficient 16-bit engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Four (4) 36-bit accumulators including extension bits 16-bit bidirectional shifter Parallel instruction set with uni.

Motorola Inc

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Datasheet Details

Part number	DSP56857
Manufacturer	Motorola Inc
File Size	1.01 MB
Description	120 MIPS Hybrid Processor
Datasheet	DSP56857 Datasheet
Additional preview pages of the DSP56857 datasheet.

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Full PDF Text Transcription

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56857 Data Sheet Technical Data www.DataSheet4U.com 56800E 16-bit Digital Signal Controllers DSP56857 Rev. 6 01/2007 freescale.com www.DataSheet4U.

Published: Apr 3, 2005 |