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MCM63P531 - 32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Description

Pin Locations 85 84 Symbol ADSC ADSP Type Input Input Description Synchronous Address Status Controller: Initiates READ, WRITE, or chip deselect cycle.

chip deselect does not occur when ADSP is

Features

  • e b Write Byte c Write Byte d Write All Bytes Write All Bytes SGW H H H H H H H L SW H L L L L L L X SBa X H L H H H L X SBb X H H L H H L X SBc X H H H L H L X SBd X H H H H L L X DC.

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Datasheet Details

Part number MCM63P531
Manufacturer Motorola
File Size 334.49 KB
Description 32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
Datasheet download datasheet MCM63P531 Datasheet
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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63P531/D Advance Information MCM63P531 32K x 32 Bit Pipelined BurstRAM™ Synchronous Fast Static RAM The MCM63P531 is a 1M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, and Pentium™ microprocessors. It is organized as 32K words of 32 bits each, fabricated using high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
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