MCM63P631A - 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Description

Pin Locations 85 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, is used to latch a new external address.

Used to initiate a READ, WRITE or chip deselect.

chip dese

Features

rite Byte c Write Byte d Write All Bytes Write All Bytes SGW H H H H H H H L SW H L L L L L L X SBa X H L H H H L X SBb X H H L H H L X SBc X H H H L H L X SBd X H H H H L L X MCM63P631A 6.

Motorola

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Datasheet Details

Part number	MCM63P631A
Manufacturer	Motorola
File Size	228.58 KB
Description	64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
Datasheet	MCM63P631A Datasheet
Additional preview pages of the MCM63P631A datasheet.

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Full PDF Text Transcription

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63P631A/D Product Preview MCM63P631A 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM63P631A is a 2M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, and Pentium™ microprocessors. It is organized as 64K words of 32 bits each. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

Published: Apr 30, 2005 |