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MCM63P736 - 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

General Description

Pin Locations 4B Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address.

Used to initiate a READ, WRITE, or chip deselect.

Key Features

  • us Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: these pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MCM63P733A 128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P531 32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P631 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P631A 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P636 64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63P736/D Product Preview 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM63P736 and MCM63P818 are 4M bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors. The MCM63P736 is organized as 128K words of 36 bits each and the MCM63P818 is organized as 256K words of 18 bits each. These devices integrate input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).