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MCM63P631 - 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

General Description

Pin Locations 85 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, is used to latch a new external address.

Used to initiate a READ, WRITE or chip deselect.

chip dese

Key Features

  • rite All Bytes Write All Bytes SGW H H H H H H H L SW H L L L L L L X SBa X H L H H H L X SBb X H H L H H L X SBc X H H H L H L X SBd X H H H H L L X MCM63P631 6.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MCM63P631A 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P636 64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P531 32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P733A 128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P736 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63P631/D Advance Information MCM63P631 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM63P631 is a 2M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, and Pentium™ microprocessors. It is organized as 64K words of 32 bits each. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.