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MCM63P818 - 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Description

Pin Locations 4B Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address.

Used to initiate a READ, WRITE, or chip deselect.

Features

  • us Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: these pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte.

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Datasheet Details

Part number MCM63P818
Manufacturer Motorola
File Size 315.65 KB
Description 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
Datasheet download datasheet MCM63P818 Datasheet
Additional preview pages of the MCM63P818 datasheet.

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Full PDF Text Transcription

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63P736/D Product Preview 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM63P736 and MCM63P818 are 4M bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors. The MCM63P736 is organized as 128K words of 36 bits each and the MCM63P818 is organized as 256K words of 18 bits each. These devices integrate input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
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